Artificial intelligence has become one of the most demanding workloads in the history of computing, and its appetite shows no sign of slowing. Behind every chatbot response, image generator output, and large-model training run sits a staggering amount of data that must move between processors, memory banks, and servers. Researchers at Zhejiang University now report a step toward meeting that demand at the physical layer: a scalable silicon photonic interconnect architecture that achieves an aggregate bandwidth of 3.2 terabits per second in the O-band, a wavelength window prized for optical communications. The work, published in PhotoniX Synergy, describes a complete transceiver circuit that combines hybrid wavelength-port multiplexing, low-crosstalk multiplexing and demultiplexing, and adaptive wavelength stabilization, offering what the team describes as a scalable pathway toward terabit-scale optical input and output for next-generation AI computing systems.
The fundamental problem the researchers set out to address is a familiar one in high-performance computing: electrical interconnects, the copper links that carry data between chips, boards, and racks, are struggling to keep pace with the traffic that modern AI clusters generate. As models grow and systems scale across thousands of accelerators, the energy and bandwidth constraints of moving bits over copper become increasingly punishing. Silicon photonics offers a compelling alternative by encoding data onto light and guiding it through waveguides fabricated on a silicon chip, where distances can be spanned with far lower loss and far higher bandwidth density. Optical interconnects promise to relieve the data-movement bottleneck that increasingly dominates both the performance and the power budget of large-scale AI infrastructure.
Yet scaling an optical link from tens of gigabits to terabits per second on a single silicon platform is far from straightforward. The dominant technique for multiplying capacity, wavelength-division multiplexing, packs many independent data channels onto slightly different wavelengths of light traveling through the same waveguide, much like several radio stations broadcasting on adjacent frequencies. As the number of channels grows, engineers must contend with three interlocking difficulties: channel density, because each wavelength requires its own multiplexing and demultiplexing hardware; crosstalk, because imperfect filters allow light from one channel to leak into its neighbors and corrupt the signal; and wavelength stability, because the tiny resonant structures that select individual wavelengths drift with temperature and fabrication variations. Any architecture hoping to reach terabit scale must solve all three problems at once, and this is precisely the challenge the Zhejiang University team took on.
Their solution begins with a heterogeneous multiplexer and demultiplexer design that deliberately assigns different jobs to the transmit and receive sides of the link. At the transmitter, the architecture employs broadband lattice-filter-based multiplexers, a class of optical filters built from cascaded interferometric stages that can combine many wavelengths with wide operating tolerance and well-controlled passbands. At the receiver, the design switches to compact Vernier dual-microring demultiplexers, which exploit the slightly mismatched free spectral ranges of paired ring resonators to separate channels using far less chip area than conventional filter banks. By pairing these two complementary technologies, the researchers report that the architecture balances the competing demands of bandwidth, physical footprint, insertion loss, and inter-channel crosstalk, avoiding the trade-offs that often force designers to sacrifice one of these metrics for another.
The second pillar of the design is what the team calls hybrid wavelength-port multiplexing, a strategy that multiplies capacity along two independent axes simultaneously. Wavelength multiplexing, as the name suggests, stacks many data channels onto distinct colors of light, while port multiplexing duplicates the approach across multiple physical waveguide ports on the chip. Because these two dimensions are largely independent, the aggregate bandwidth scales as the product of the number of wavelengths per port and the number of ports, allowing the system to reach terabit-level totals without requiring an unmanageable number of wavelengths crammed onto a single waveguide. This is what makes the architecture genuinely scalable in the eyes of its designers: capacity growth does not have to come at the price of exploding channel density or escalating system complexity.
The corresponding author, Jianyi Yang, a professor at Zhejiang University, framed the motivation in practical terms. The goal, he said, was to make terabit-scale silicon photonic interconnects more scalable and robust. By combining wavelength and port multiplexing with complementary multiplexer and demultiplexer designs, he explained, the team can scale the aggregate bandwidth while maintaining manageable channel density and system complexity. That phrasing captures a subtle but important engineering insight: raw bandwidth figures are meaningless if achieving them requires exotic packaging, extreme thermal control, or filter structures whose losses erase the benefits of optical transmission. The architecture is designed so that each increment of capacity arrives with a proportionate, and tolerable, increase in hardware.
Scalability alone, however, would be fragile without the third element of the design: wavelength stabilization. Microring resonators are extraordinarily compact and efficient wavelength selectors, but their resonant wavelengths depend sensitively on temperature and on tiny manufacturing deviations, which can shift a channel’s operating point away from its assigned grid and degrade the link. To keep the channels locked, the researchers implemented an FPGA-assisted adaptive wavelength-locking framework built on closed-loop thermo-optic control. Small heaters integrated with the photonic devices allow their resonances to be tuned electrically, and a feedback algorithm running on a field-programmable gate array continuously monitors the optical signals and adjusts the heating in real time, tracking and stabilizing the resonant wavelengths even as conditions change. The result is an optical link that can hold its channels on target through the thermal fluctuations and slow drifts that would otherwise derail a densely multiplexed system.
Bin Zhang, a doctoral student at Zhejiang University and first author of the paper, emphasized why this control layer matters so much. Wavelength stability, he said, is particularly important as resonator-based photonic systems become more highly integrated. The FPGA-assisted adaptive wavelength-locking framework, he noted, provides a flexible way to compensate for wavelength drift and helps improve the robustness of the optical interconnect. The word adaptive is doing real work here: rather than calibrating each device once at the factory, the system continuously re-tunes itself during operation, which is exactly the kind of self-correcting behavior that large, densely integrated photonic circuits require if they are to be deployed in the noisy, thermally dynamic environment of a data center.
The demonstrated result is a 3.2-terabit-per-second PAM4 silicon photonic circuit operating in the O-band, the wavelength region around 1310 nanometers that has long served as a workhorse for short-reach optical communications. PAM4, or four-level pulse amplitude modulation, doubles the information carried per symbol compared with simpler on-off signaling, so the recorded aggregate figure reflects both the dense wavelength and port multiplexing of the architecture and the efficiency of the modulation format itself. An experimental study of this kind demonstrates the complete chain of a working transceiver: data encoded onto light at the transmit side, multiplexed across many wavelengths and ports, carried through the optical channel, separated at the receive side by the dual-microring demultiplexers, and held stable throughout by the adaptive locking loop. Declaring no conflicts of interest, the authors present the work as a proof of architectural principle rather than a finished commercial product.
The broader significance of the result lies in what it suggests about the trajectory of AI hardware. As machine learning systems grow, the energy spent moving data between processors already rivals or exceeds the energy spent computing on that data, which has pushed the industry toward optical input and output co-packaged with switching silicon. An architecture that scales bandwidth through two independent multiplexing dimensions, while keeping crosstalk, footprint, and loss in check and compensating for wavelength drift automatically, addresses the specific pain points that have limited the density of previous designs. For hyperscale data centers, where a single training cluster may require thousands of terabit-class links, even incremental improvements in per-link bandwidth, power efficiency, and robustness compound into substantial savings. If approaches of this kind continue to mature, the copper highways that currently bind AI systems together may give way to grids of light, with silicon photonic transceivers like this 3.2-terabit demonstration pointing the way toward the terabit-scale fabric that next-generation computing will demand.
Subject of Research: Scalable silicon photonic interconnect architecture for high-bandwidth AI computing
Article Title: Scalable 3.2-Tb/s silicon photonic interconnect targets next-generation AI computing
Article References: Scalable 3.2-Tb/s silicon photonic interconnect targets next-generation AI computing. (n.d.). Original publication
Image Credits: AI Generated
DOI: Not provided
Keywords: silicon photonics, optical interconnect, wavelength-division multiplexing, artificial intelligence, data centers, microring resonators, PAM4 modulation, wavelength stabilization, FPGA control, photonic integrated circuits, bandwidth, O-band
